The subject matter relates to a semiconductor design technology, and more particularly, to an output enable signal generating circuit and method for performing a domain crossing operation in a semiconductor memory device.
In general, a semiconductor memory device, such as a Double Data Rate Synchronous DRAM (DDR SDRAM) device, receives data from the outside of the device in response to an external clock signal, and outputs data stored therein in response to an internal clock signal. That is, the internal clock signal, not the external clock signal, is used for a data processing operation within a semiconductor memory device. From the perspective of data, the input of data is synchronized with the external clock signal and is output in synchrony with the internal clock signal. A situation in which a certain clock signal for data transfer changes to another is called a “domain crossing”.
A semiconductor memory device is provided with various circuits to carry out such a domain crossing operation. One of these circuits is an output enable signal generating circuit. In the output enable signal generating circuit, a domain crossing occurs between a read command transferred in synchrony with an external clock signal and an internal clock signal, in order to generate an output enable signal. Thus, the domain-crossed output enable signal allows data and commands provided to the device to be synchronized with the external clock signal and for data to be output in accordance with a CAS latency. The CAS latency is a unit of time corresponding to one period of the external clock signal, and indicates a period of time from when the read command is input to when data is output.
Meanwhile, the semiconductor memory device also has an internal clock signal generating circuit to compensate for skew that may occur between an external clock signal and an internal clock signal due to delay elements within the device, such as a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL). In the following description, a DLL clock signal generated by a DLL will be used for illustrative purposes.
FIG. 1 is a block diagram showing an output signal generating circuit in a conventional semiconductor memory device.
Referring to FIG. 1, the output enable signal generating circuit includes a counter reset signal generator 110, an initialization unit 120, a DLL clock counter 130, a delay model 140, an external clock counter 150, a latch 160, and a comparator 170.
The counter reset signal generator 110 generates a first reset signal RSTB_DLL, to reset the DLL clock counter 130, in response to a reset signal RSTB and a DLL clock signal CLK_DLL. Here, the reset signal RSTB is generated by decoding plural external commands (e.g., /RAS, /CAS, /CS, and /WE).
The initialization unit 120 provides the DLL clock counter 130 with an initial count value corresponding to a CAS latency CL. Table 1 below lists initial count values that correspond to CAS latencies CL3 to CL6, and their corresponding output signals S<0:2> from the initialization unit 120. Initial count values corresponding to the CAS latencies CLs may vary depending on the design.
TABLE 1CLInitial count valueS<2>S<1>S<0>35101441005301162010
The DLL clock counter 130 is reset in response to the first reset signal RSTB_DLL, and executes a counting operation in response to a DLL clock signal CLK_DLL, starting from an initial count value corresponding to the output signal S<0:2> provided by the initialization unit 120. For example, suppose that ‘5’ is set for an initial count value, corresponding to CL3. Then, the DLL clock counter 130 generates, in response to the DLL clock signal CLK_DLL, a DLL clock count value CNT_DLL<0:2> counting from 3. As another example, suppose that ‘4’ is set for an initial count value corresponding to the CL4. Then, the DLL clock counter 130 generates, in response to the DLL clock signal CLK_DLL, a DLL clock count value CNT_DLL<0:2> counting from 4. That is to say, the DLL clock counter 130 executes a counting operation in response to the DLL clock signal CLK_DLL, starting from a preset initial count value in accordance with a CL.
The delay model 140 delays the first reset signal RSTB_DLL to compensate for a phase difference between an external clock signal CLK_EXT and its corresponding DLL clock signal CLK_DLL, and outputs it as a second reset signal RSTB_EXT.
The external clock counter 150 is reset to an initial count value in response to the second reset signal RSTB_EXT, and executes a counting operation in response to the external clock signal CLK_EXT. Here, the initial count value for the external clock counter 150 is set to 0.
The latch 160 latches, in response to a read command RD, an external clock count value CNT_EXT<0:2>, which is an output signal from the external clock counter 150, and outputs the latched external clock count value CNT_LAT<0:2>.
The comparator 170 compares the DLL clock count value CNT_DLL<0:2> with the latched external clock count value CNT_LAT<0:2>, making an output enable signal OE active when those two values are equal to each other. Here, the output enable signal OE is a signal synchronized with the DLL clock signal CLK_DLL, and conveys information about the CAS latency CL. Thus, the activation timing of the output enable signal OE varies depending on the CAS latency CL. As information, the output enable signal OE has a pulse width corresponding to burst length information, and is used for outputting data.
FIG. 2 is a timing diagram showing an operation timing of the output enable signal generating circuit depicted in FIG. 1. For convenience of explanation, “CL4” indicates that a CAS latency CL is 4, and similarly “CL6” indicates that a CAS latency CL is 6.
First, a case where the CAS latency CL is 4 (CL4) is explained.
An initial count value of the initialization unit 120 is set to 4, in accordance with Table 1 above. When the first reset signal RSTB_DLL has a logic ‘high’ level, the DLL clock counter 130 executes a counting operation in response to the DLL clock signal CLK_DLL starting from 4 as the initial count value, and outputs a DLL clock count value CNT_DLL<0:2>.
Next, the delay model 140 outputs a second reset signal RSTB_EXT by imposing a delay time D on the first reset signal RSTB_DLL. The external clock counter 150, which has been released from reset in response to the second reset signal RSTB_EXT switching to a logic ‘high’ level, outputs, in response to the external clock signal CLK_EXT, an external clock count value CNT_EXT<0:2>, counting from an initial count value of 0.
When a read command RD is input, the latch 160 latches an external clock count value CNT_EXT<0:2>, i.e. 3, in response to a read command RD that is applied at the timing when the external clock signal CLK_EXT is labeled 0, and outputs it as a latched external clock count value CNT_LAT<0:2>. The comparator 170 compares the DLL clock count vale CNT_DLL<0:2> with the latched external count value CNT_LAT<0:2>, to activate an output enable signal OE when those two count values are equal to each other, that is, when the DLL clock count value CNT_DLL<0:2> becomes 3. The output enable signal OE so generated is used for outputting data synchronized with the timing corresponding to the fourth clock period of CLK_EXT after the read command RD.
Next, a case where the CAS latency CL is 5 (CL5) is explained.
An initial count value of the initialization unit 120 is set to 3, in accordance with Table 1 above. When the first reset signal RSTB_DLL is activated to a logic ‘high’ level, the DLL clock counter 130 executes a counting operation in response to the DLL clock signal CLK_DLL starting from 3 as the initial count value, and outputs a DLL clock count value CNT_DLL<0:2>. The external clock counter 150, which has been released from reset in response to the second reset signal RSTB_EXT, outputs an external clock count value CNT_EXT<0:2>, counting from an initial count value of 0.
When a read command RD is input, the latch 160 latches an external clock count value CNT_EXT<0:2>, i.e. 3, and outputs it as a latched external clock count value CNT_LAT<0:2>. The comparator 170 compares the DLL clock count vale CNT_DLL<0:2> with the latched external count value CNT_LAT<0:2>, to activate an output enable signal OE when those two count values are equal to each other, that is, when the DLL clock count value CNT_DLL<0:2> becomes 3.
Lastly, a case where the CAS latency CL is 6 (CL6) is discussed.
An initial count value of the initialization unit 120 is set to 2, in accordance with Table 1 above. The DLL clock counter 130 executes a counting operation in response to the DLL clock signal CLK_DLL starting from 2 as the initial count value, and outputs a DLL clock count value CNT_DLL<0:2>, which is incremented by the counting operation. The external clock counter 150 outputs an external clock count value CNT_EXT<0:2>, counting from an initial count value of 0.
When a read command RD is input, the latch 160 latches an external clock count value CNT_EXT<0:2>, i.e. 3, and outputs it as a latched external clock count value CNT_LAT<0:2>. The comparator 170 compares the DLL clock count value CNT_DLL<0:2> with the latched external count value CNT_LAT<0:2>, to provide an output enable signal OE activated when those two count values are equal to each other, that is, when the DLL clock count value CNT_DLL<0:2> becomes 3.
Meanwhile, the read command RD can be input at a fixed interval tCCD. Here, tCCD defines a minimum time gap between consecutive read commands RD. For example, for a DDR2 device, two clock periods of the external clock signal CLK_EXT are designated as tCCD, while for a DDR3 device, three clock periods of the external clock signal CLK_EXT are designated as tCCD.
The output enable signal generating circuit with the conventional configuration as discussed above exhibits a problem as shown in FIG. 3, regarding read commands RD1 and RD2 that are applied at the interval of tCCD.
FIG. 3 is a timing diagram for a case where the read command RD of FIG. 2 is repeated at the interval of tCCD. For convenience of explanation, a DDR2 device is used by way of example. In this case, tCCD is two clock periods of the external clock signal CLK_EXT. That is, if a first read command RD1 is applied at the timing where the external clock signal CLK_EXT is labeled 0, then a second read command RD2 can be applied as early as when the external clock signal CLK_EXT is labeled 2.
First, a case where a CAS latency CL is 4 will be explained.
An initial count value of the initialization unit 120 is set to 4. When the first reset signal RSTB_DLL has a logic ‘high’ level, the DLL clock counter 130 executes a counting operation in response to the DLL clock signal CLK_DLL starting from 4 as the initial count value, and outputs a DLL clock count value CNT_DLL<0:2>.
Next, the delay model 140 outputs a second reset signal RSTB_EXT by imposing a delay time D on the first reset signal RSTB_DLL. The external clock counter 150, which has been released from reset in response to the second reset signal RSTB_EXT switching to a logic ‘high’ level, outputs, in response to the external clock signal CLK_EXT, an external clock count value CNT_EXT<0:2>, counting from an initial count value of 0. When a read command RD1 is input, the latch 160 latches an external clock count value CNT_EXT<0:2>, i.e. 3, when the first read command RD1 is input at the timing when the external clock signal CLK_EXT is labeled 0, and outputs it as a latched external clock count value CNT_LAT<0:2>.
Since tCCD is two clock periods of CLK_EXT, the second read command RD2 can be input at the timing when the external clock signal CLK_EXT is labeled 2, before the DLL clock count value CNT_DLL<0:2> becomes 3. Then, the latch 160 latches an external clock count value CNT_EXT<0:2>, i.e., 5, in response to the second read command RD2, and outputs it as a latched external clock count value CNT_LAT<0:2>.
Thus, the comparator 170 compares the DLL clock count value CNT_DLL<0:2> with the latched external clock count value CNT_LAT<0:2>, and activates an output enable signal OE at the timing when those two count values become equal to each other, that is, when the DLL clock count value CNT_DLL<0:2> becomes 5. As can be seen in FIG. 3, the output enable signal OE ignores the first read command RD1, but becomes activated in response to the second read command RD2. This means that the output enable signal OE is not activated at a desired time corresponding to the read command RD1, and thus, a semiconductor memory device outputs data without regard to the CAS latency CL 4. In other words, the semiconductor memory device has malfunctioned.
Next, in a case where a CAS latency CL is 5, the latch 160 latches 3 corresponding to the first read command RD1 first, and then latches 5 corresponding to the second read command RD2, as in the case where a CAS latency CL is 4. Similarly, the output enable signal OE is not activated at a desired time corresponding to the read command RD1.
For the conventional output enable signal generating circuit as noted earlier, if read commands are input consecutively, especially when the second read command is input before an external clock count value CNT_LAT<0:2> latched in response to the first read command is compared with a desired DLL clock count value CNT_DLL<0:2> at the comparator 170, the output enable signal OE will not be activated at a desired time. In other words, if a CAS latency CL is greater than tCCD, the output enable signal OE canis not activated at a desired time. That is, the output enable signal OE is not activated corresponding to a desired CAS latency CL, and an output enable signal OE causes malfunctioning of a semiconductor memory device and further impairs the precision and reliability of the device.
Furthermore, as the operating frequency of semiconductor memory devices continue to increase, nowadays into the GHz, a CAS latency CL increases more or more accordingly. Accordingly, the aforementioned problems will occur more frequently.